There has been provided a semiconductor module that a semiconductor device is mounted on a multi-layer substrate. A substrate structure which can be used as the multi-layer substrate for configuring such semiconductor module is disclosed in Japanese Patent Application Laid-Open No. 164150 (1994).
A capacitive element layer is provided within the multi-layer substrate. The capacitive element layer has a dielectric layer and a pair of internal electrodes disposed so as to face with each other with the dielectric layer being interposed therebetween. The dielectric layer is selectively provided only at the substrate area that the capacitive element layer is provided. Terminal electrodes are provided on a surface of the multi-layer substrate. One terminal electrode is provided immediately above the internal electrode, and electrically connected via a via hole formed at the multi-layer substrate to the internal electrode. The other terminal electrode is drawn to a side of the multi-layer substrate, and is connected to a side electrode which is formed at the side of the multi-layer substrate.
In the semiconductor module used in a high frequency band (1 MHz to dozens GHz), improvements in high frequency characteristic become a problem. Examples of the improvements in high frequency characteristic include easy design of cut-off frequency (i.e., a frequency serving as a boundary between a passing band and an attenuation band), widening of the band, improvements in distortion characteristic, reduction in parasitic capacitance component (including a parasitic inductance) caused by mounting, and the like.
As described above, the high frequency characteristic can be improved to a certain extent in the semiconductor module that a semiconductor device is mounted on a conventional multi-layer substrate (Japanese Patent Application Laid-Open No. 164150 (1994)).
In such semiconductor module, however, height variations occur between the terminal electrode which is placed above the capacitive element layer (which is electrically connected via a via hole to the internal electrode) and the terminal electrode which is not placed above the capacitive element layer (which is electrically connected via a internal wiring to the side electrode).
In a case of structure that three or less connected portions between the semiconductor device and the multi-layer substrate are provided (i.e., the number of terminal electrodes is three or less), even if the height variations are generated, a flat surface connecting the connected portions always exists. Nevertheless, in a case of structure that four or more connected portions are provided (i.e., the number of terminal electrodes is four or more), if the height variations are generated, a flat surface connecting the connected portions cannot be formed. As a result, when the semiconductor device is flip-chip-bonded to the multi-layer substrate with four or more connected portions (four or more terminal electrodes), a clearance may be generated between the semiconductor device and the terminal electrode due to the above-described height variations of the terminal electrodes. Thus, it is difficult to perform stable flip-chip-bonding of the semiconductor device.
Furthermore, in accordance with the semiconductor module, the height variations may be larger due to the following reasons. Namely, in order to reduce a parasitic capacitance component which presents a problem in the semiconductor module, the semiconductor device must be connected to the capacitive element layer at a distance that is as short as possible. In order to perform such short distance connection, it is proposed that a length of a via hole (which connects an electrode layer constituting the capacitive element layer to a terminal electrode provided at the surface of multi-layer substrate) is made short. In order to make the length of the via hole short, a thickness of the substrate area that the via hole is formed must be thin. Nevertheless, the via hole is placed above the capacitive element layer, and the substrate area that the via hole is formed refers to as the substrate area that the capacitive element layer is formed. For this reason, if the thickness of the substrate area that the via hole is formed is made thin, a ratio of thickness of capacitive element layer to a total thickness of the substrate area becomes high. As a result, the height variations caused by the capacitive element layer become larger.